Nonvolatile memory devices such as Electrically Programmable Read Only Memories (“EPROMs”), Electrically Erasable Programmable Read Only Memories (“E2PROMs”), and flash EEPROMs include an array of nonvolatile memory cells and supporting periphery circuitry for accessing the array. A nonvolatile memory cell typically behaves like a field effect transistor and includes a select (or control) gate that controls the reading and writing of data to the memory cell and a floating gate that traps charge to alter the datum or data stored by the memory cell.
As charge is added to the floating gate of a memory cell, the threshold voltage Vt of the memory cell increases, and the memory cell drain current ID (“cell current”) decreases. The memory cell threshold voltage Vt is related to the memory cell drain current ID by the expression:IDαGm×(VG−Vt)for VD>VG−Vtwherein Gm is the transconductance of the memory cell; VG is the memory cell gate voltage; VD is the memory cell drain voltage; and Vt is the memory cell threshold voltage.
Given this relationship, there are a number of prior art methods for sensing the amount of charge stored on of the floating gate of the memory cell, including the following:                1) sensing the cell current of a memory cell when a constant voltage is applied to the select gate of the memory cell;        2) sensing the amount of voltage required at the select gate to give rise to an expected cell current for the memory cell;        3) sensing a voltage drop across a load that is coupled to the drain of the memory cell when a constant voltage is applied to the select gate of the memory cell, wherein the cell current determines the amount of the voltage drop across the load; and        4) sensing the amount of voltage required at the select gate to give rise to an expected voltage drop across a load that is coupled to the drain of the memory cell.        
Once sensed, the amount of charge determined to be stored on the floating gate is decoded to correspond to one of n possible states, n being two or more, and the binary representation (log2n) of the determined state is output. One disadvantage of the above-described methods, all of which require an active cell current, is that a relatively large amount of current is required for sensing each cell, which reduces the maximum number of cells that may be sensed in parallel.
FIG. 1 shows a prior sensing system 5 that is used to sense the state of, and therefore the data stored by, nonvolatile memory cell 10. Nonvolatile memory cell 10 includes a select gate SG, a floating gate FG, a source S, and a drain D. Memory cell 10 operates as a field effect transistor (FET) having a variable threshold voltage Vt that is changed by adding and removing charge from the floating gate FG. Because memory cell 10 operates as a field effect transistor, the electrodes shown in FIG. 1 as the drain D and the source S may interchangeably be used as either source or drain depending upon the particular configuration of memory cell 10 and the operating characteristics applied thereto.
As shown, the prior art sensing system 5 detects the amount of cell drain current ID that results from applying a read voltage VG to the select gate SG of memory cell 10. Depending upon the amount of charge stored on the floating gate FG of memory cell 10, the cell current ID may vary anywhere from zero to approximately 100 microamperes when the read voltage VG is applied to select gate SG.
The select gate SG of memory cell 10 is coupled to a wordline (not shown) to receive the read voltage VG, the drain of memory cell 10 is coupled to a bitline (not shown) to which sensing system 5 is coupled to detect the strength of the cell current ID, and the source of memory cell 10 is coupled to a ground potential VSS to give rise to the cell current ID that flows from the drain to the source as shown. Thus, memory cell 10 operates as a pull-down device.
A corresponding pull-up device is found in column load circuit 19. Column load circuit 19 is shown as including a transistor 20 that is biased to operate as a pull up device by a gate voltage Vbias. A drain bias circuit 12 is coupled between the drain D of memory cell 10 and column load circuit 19 to ensure that the drain D of memory cell 10 does not drop below a predetermined voltage (e.g. approximately one volt). Drain bias circuit 12 is shown as including a cascode transistor 15 and feedback circuitry 17. Feedback circuitry 17 provides a necessary voltage to the gate of transistor 15 such that the drain D of memory cell 10 does not drop below the predetermined voltage.
Once the read voltage VG is applied to the select gate SG of memory cell 10, the amount of charge trapped on floating gate FG determines the strength of the cell current ID and the strength of the pull-down provided by memory cell 10. Typically, if the memory cell 10 is erased, memory cell 10 acts as a strong pull-down device to overcome the pull-up provided by column load circuit 19 such that the negative input of a differential sense amplifier 25 is discharged towards ground. Sense amplifier 25 compares the voltage at its negative input to the voltage at its positive input, which is supplied by a reference circuit 30. According to common prior techniques, reference circuit 30 includes a reference cell (not shown) that has its floating gate charged to a predetermined level coupled to a drain bias circuit and column load circuit identical to those shown of sensing system 5.
Using the sensing scheme embodied by sensing system 5 requires a relatively large amount of current to read memory cell 10. For example, each of the memory cell 10, the drain bias circuit 12, and the sense amplifier 25 require current for operation and therefore result in power consumption. The amount of power consumption required by these components of sensing system 5 results in the ability of sensing system 5 to sense relatively few memory cells (e.g. 16 or 32) in parallel.